A seasoned Design Verification Engineer with over 10 years of experience to join their team in San Jose. The ideal candidate will have extensive expertise in PCle protocol and hands-on experience in ASIC/FPGA design verification. Responsibilities include developing and executing test plans, creating and maintaining verification environments using System Verilog/UVM, and debugging complex design issues. The role demands proficiency in scripting languages (Python, Perl) and strong analytical and problem-solving skills. Familiarity with modern EDA tools and methodologies is essential. Excellent communication and teamwork abilities are required to collaborate effectively with cross-functional teams. #J-18808-Ljbffr Xlysi LLC.
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